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Freescale Semiconductor Hardware Specification
Document Number: MCF5275EC Rev. 2, 08/2006
MCF5275 Integrated Microprocessor Family Hardware Specification
by: Microcontroller Division
The MCF5275 family is a highly integrated implementation of the ColdFire(R) family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions characteristics of the MCF5275 family. The MCF5275 family includes the MCF5275, MCF5275L, MCF5274 and MCF5274L microprocessors. The differences between these parts are summarized in Table 1. This document is written from the perspective of the MCF5275 and unless otherwise noted, the information applies also to the MCF5275L, MCF5274 and MCF5274L. The MCF5275 family delivers a new level of performance and integration on the popular version 2 ColdFire core with up to 159 (Dhrystone 2.1) MIPS @ 166MHz. These highly integrated microprocessors build upon the widely used peripheral mix on the popular MCF5272 ColdFire microprocessor (10/100 Mbps Ethernet MAC and USB device) by adding a second 10/100 Mbps Ethernet MAC (MCF5274 and MCF5275) and hardware encryption (MCF5275L and MCF5275).
Contents
1 2 3 4 5 6 7 8 9 10 MCF5275 Family Configurations . . . . . . . . . . . . . . . . . . . 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Design Recommendations . . . . . . . . . . . . . . . . . . . . . . . 9 Mechanicals/Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Preliminary Electrical Characteristics . . . . . . . . . . . . . . 18 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
(c) Freescale Semiconductor, Inc., 2006. All rights reserved. * Preliminary--Subject to Change Without Notice
MCF5275 Family Configurations
In addition, the MCF5275 family features an enhanced multiply accumulate unit (EMAC), large on-chip memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory controller. These devices are ideal for cost-sensitive applications requiring significant control processing for file management, connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security, imaging, networking, gaming, and medical. This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support. To locate any published errata or updates for this document, refer to the ColdFire products website at http://www.freescale.com/coldfire.
1
MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module
ColdFire Version 2 Core with EMAC (Enhanced Multiply-Accumulate Unit) System Clock Performance (Dhrystone 2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) DDR SDRAM Controller Fast Ethernet Controller (FEC) Watchdog Timer Module (WDT) 4-channel Programmable Interval Timer Module (PIT) 32-bit DMA Timers USB QSPI UART(s) I2 C 2 x x x x 1 x x 4 x x 3 x 4 x x x x -- 2 x x x x 1 x x 4 x x 3 x 4 x x x x x
MCF5274L
x
MCF5275L
x
MCF5274
x
MCF5275
x
up to 166 MHz up to 159 16 Kbytes (configurable) 64 Kbytes 2 x x x x 2 x x 4 x x 3 x 4 x x x x -- 2 x x x x 2 x x 4 x x 3 x 4 x x x x x
PWM General Purpose I/O Module (GPIO) CIM = Chip Configuration Module + Reset Controller Module Debug BDM JTAG - IEEE 1149.1 Test Access Port Hardware Encryption Package
196 MAPBGA 196 MAPBGA 256 MAPBGA 256 MAPBGA
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 2 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Block Diagram
2
Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
EIM (To/From SRAM backdoor) CHIP SELECTS
DDR QSPI I2C_SDA I2C_SCL
Arbiter
INTC0
INTC1
EBI
TXDx RXDx RTSx CTSx
(To/From PADI)
FAST ETHERNET CONTROLLER (FEC0) PADI - Pin Muxing FAST ETHERNET CONTROLLER (FEC1) UART 0 UART 1 UART 2 I2 C QSPI SDRAMC
DTOUTx DTINx FEC0 FEC1 USB PWMx D[31:16] A[23:0] R/W CS[3:0] TA
(To/From PADI)
(To/From PADI)
DTIM 0 4 CH DMA
DTIM 1
DTIM 2
DTIM 3
JTAG TAP
BDM
DREQ[1:0]
DACK[3:0]
V2 ColdFire CPU
DIV EMAC
JTAG_EN TRST TCLK TMS TDI
MUX
JTAG_EN
TDO TSIZ[1:0]
(To/From PADI) (To/From PADI)
4 CH PWM
64 Kbytes SRAM (8Kx16)x4
16 Kbytes CACHE (1Kx32)x4 PORTS (GPIO) CIM
TEA BS[3:2]
Watchdog Timer
(To/From Arbiter backdoor)
MDHA
RNGA Cryptography Modules
SKHA
USB 2.0 Full Speed
Edge Port
PLL CLKGEN
PIT0
PIT1
PIT2
PIT3
(To/From PADI) (To/From INTC)
Figure 1. MCF5275 Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 3
Features
3 4
Features Signal Descriptions
For a detailed feature list see the MCF5275 Reference Manual (MCF5275RM).
This section describes signals that connect off chip, including a table of signal properties. For a more detailed discussion of the MCF5275 signals, consult the MCF5275 Reference Manual (MCF5275RM). Table 2 lists the signals for the MCF5275 in functional group order. The "Dir" column is the direction for the primary function of the pin. Refer to Section 6, "Mechanicals/Pinouts," for package diagrams. NOTE In this table and throughout this document a single signal within a group is designated without square brackets (i.e., A24), while designations for multiple signals within a group use brackets (i.e., A[23:21]) and is meant to include all signals within the two bracketed numbers when these numbers are separated by a colon. NOTE The primary functionality of a pin is not necessarily its default functionality. Pins that are muxed with GPIO will default to their GPIO functionality.
Table 2. MCF5274 and MCF5275 Signal Information and Muxing
Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA MCF5274L MCF5275L 196 MAPBGA
Reset RESET RSTOUT -- -- -- -- -- -- Clock EXTAL XTAL CLKOUT -- -- -- -- -- -- -- -- -- Mode Selection CLKMOD[1:0] RCON -- -- -- -- -- -- I I N13, P13 P8 M11, N11 M6 I O O L16 M16 T12 M14 N14 P9 I O N15 N14 K12 L12
External Memory Interface and Ports A[23:21] PADDR[7:5] CS[6:4] -- O A11, B11, C11 A8, B8, C8
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 4 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA A12, B12, C12, A13, B13, C13, A14, B14, C14, B15, C15, B16, C16, D14, D15, E14:16, F14:16 M1, N1, N2, N3, P1, P2, R1, R2, P3, R3, T3, N4, P4, R4, T4, N5 M3, R5 K1 L13 T8 P7 D16 G16 L4 P6 MCF5274L MCF5275L 196 MAPBGA B9, D9, C9, C10, B10, A11, C11, B11, A12, D11, C12, B13, C13, D12, E11, D13, E12, F11, D14, E13, F13 J3, L1, K2, K3, M1, L2, L3, L4, K4, J4, M2, N1, N2, M3, M4, N3 K1, L5 H4 K14 -- L6 B14 E14 H2 --
A[20:0]
--
--
--
O
D[31:16]
--
--
--
O
BS[3:2] OE TA TEA R/W TSIZ1 TSIZ0 TS TIP
PBS[3:2] PBUSCTL[7] PBUSCTL[6] PBUSCTL[5] PBUSCTL[4] PBUSCTL[3] PBUSCTL[2] PBUSCTL[1] PBUSCTL[0]
CAS[3:2] -- -- DREQ1 -- DACK1 DACK0 DACK2 DREQ0
-- -- -- -- -- -- -- -- --
O O I I O O O O O
Chip Selects CS[7:1] PCS[7:1] -- -- O D10:13, E13, F13, N7 R6 D8, A9, A10, D10, B12, C14, P4 N5
CS0
--
--
--
O
DDR SDRAM Controller DDR_CLKOUT DDR_CLKOUT SD_CS[1:0] SD_SRAS SD_SCAS SD_WE SD_A10 SD_DQS[3:2] SD_CKE SD_VREF -- -- PSDRAM[7:6] PSDRAM[5] PSDRAM[4] PSDRAM[3] -- PSDRAM[2:1] PSDRAM[0] -- -- -- CS[3:2] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O O O O O O I/O O I T7 T6 M2, T5 L2 L1 K2 N6 M4, P5 L3 A15, T2 P6 P5 H3, M5 H1 G3 G4 N4 J2, P3 J1 A13, P2
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 5
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA MCF5274L MCF5275L 196 MAPBGA
External Interrupts Port IRQ[7:5] IRQ[4] IRQ[3:2] IRQ1 PIRQ[7:5] PIRQ[4] PIRQ[3:2] PIRQ[1] -- DREQ2 DREQ[3:2] -- FEC0 FEC0_MDIO FEC0_MDC FEC0_TXCLK FEC0_TXEN FEC0_TXD[0] FEC0_COL FEC0_RXCLK FEC0_RXDV FEC0_RXD[0] FEC0_CRS FEC0_TXD[3:1] FEC0_TXER FEC0_RXD[3:1] FEC0_RXER PFECI2C[5] PFECI2C[4] PFEC0H[7] PFEC0H[6] PFEC0H[5] PFEC0H[4] PFEC0H[3] PFEC0H[2] PFEC0H[1] PFEC0H[0] PFEC0L[7:5] PFEC0L[4] PFEC0L[3:1] PFEC0L[0] I2C_SDA I2C_SCL -- -- -- -- -- -- -- -- -- -- -- -- FEC1 FEC1_MDIO FEC1_MDC FEC1_TXCLK FEC1_TXEN FEC1_TXD[0] FEC1_COL FEC1_RXCLK FEC1_RXDV FEC1_RXD[0] FEC1_CRS PFECI2C[3] PFECI2C[2] PFEC1H[7] PFEC1H[6] PFEC1H[5] PFEC1H[4] PFEC1H[3] PFEC1H[2] PFEC1H[1] PFEC1H[0] -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I/O O I O O I I I I I G1 G2 C1 D2 F1 A5 B4 A3 B3 A4 -- -- -- -- -- -- -- -- -- -- U2RXD U2TXD -- -- -- -- -- -- -- -- -- -- -- -- I/O O I O O I I I I I O O I I A7 B7 C3 D4 G4 A6 B6 B5 C6 C7 E3, F3, F4 D3 D5, C5, D6 C4 A3 C5 C1 C3 D2 B4 B3 C4 D5 A2 D1, E3, D3 C2 D4, B1, B2 E4 -- -- -- -- I I I I G13, H16, H15 H14 J14, J13 K13 F14, G13, G14 H11 H14, H12 J13
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 6 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA E1, E2, F2 D1 B1, B2, A2 C2 MCF5274L MCF5275L 196 MAPBGA -- -- -- --
FEC1_TXD[3:1] FEC1_TXER FEC1_RXD[3:1] FEC1_RXER
PFEC1L[7:5] PFEC1L[4] PFEC1L[3:1] PFEC1L[0]
-- -- -- -- I2C
-- -- -- --
O O I I
I2C_SDA I2C_SCL
PFECI2C[1] PFECI2C[0]
U2RXD U2TXD DMA
-- --
I/O I/O
B10 C10
B7 A7
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for DREQ2, TEA for DREQ1, and TIP for DREQ0. QSPI QSPI_CS[3:2] QSPI_CS1 QSPI_CS0 QSPI_CLK QSPI_DIN QSPI_DOUT PQSPI[6:5] PQSPI[4] PQSPI[3] PQSPI[2] PQSPI[1] PQSPI[0] PWM[3:2] -- -- I2C_SCL I2C_SDA -- DACK[3:2] -- -- -- -- -- UARTs U2RXD U2TXD U2CTS U2RTS U1RXD U1TXD U1CTS U1RTS U0RXD U0TXD U0CTS PUARTH[3] PUARTH[2] PUARTH[1] PUARTH[0] PUARTL[7] PUARTL[6] PUARTL[5] PUARTL[4] PUARTL[3] PUARTL[2] PUARTL[1] -- -- PWM1 PWM0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- I O I O I O I O I O I O O O O I O
--
--
R13, N12 T14 P12 T15 T13 R12
P10, N9 N10 M9 L11 M10 L10
T9 R9 P9 R8 A9 B9 C9 D9 A8 B8 C8
-- -- -- -- A6 D7 C7 B6 A4 A5 C6
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 7
Signal Descriptions
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA D7 MCF5274L MCF5275L 196 MAPBGA B5
U0RTS
PUARTL[0]
-- USB
--
O
USB_SPEED USB_CLK USB_RN USB_RP USB_RXD USB_SUSP USB_TN USB_TP USB_TXEN
PUSBH[0] PUSBL[7] PUSBL[6] PUSBL[5] PUSBL[4] PUSBL[3] PUSBL[2] PUSBL[1] PUSBL[0]
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
I/O I I I I O O O O
G14 G15 J16 J15 L15 M13 K14 K15 L14
G11 F12 H13 J11 L14 N13 J14 J12 K13
Timers (and PWMs) DT3IN DT3OUT DT2IN DT2OUT DT1IN DT1OUT DT0IN DT0OUT PTIMERH[3] PTIMERH[2] PTIMERH[1] PTIMERH[0] PTIMERL[3] PTIMERL[2] PTIMERL[1] PTIMERL[0] DT3OUT PWM3 DT2OUT PWM2 DT1OUT PWM1 DT0OUT PWM0 U2RTS U2CTS -- -- -- -- -- -- BDM/JTAG2 DSCLK PSTCLK BKPT DSI DSO JTAG_EN DDATA[3:0] PST[3:0] -- -- -- -- -- -- -- -- TRST TCLK TMS TDI TDO -- -- -- -- -- -- -- -- -- -- -- I O I I O I O O P14 P16 R15 R16 P15 R14 P13 P12 N12 M12 K11 P11 I O I O I O I O J4 K3 J2 J3 H1 H2 H3 G3 G2 G1 F3 F4 F1 F2 E1 E2
P10, N10, P11, M7, N7, P8, L9 N11 T10, R10, T11, R11 P7, L8, M8, N8
Test
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 8 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Design Recommendations
Table 2. MCF5274 and MCF5275 Signal Information and Muxing (continued)
Signal Name GPIO Alternate1 Alternate2 Dir.1 MCF5274 MCF5275 256 MAPBGA N9 M14 MCF5274L MCF5275L 196 MAPBGA N6 --
TEST PLL_TEST
-- --
-- --
-- -- Power Supplies
I I
VDDPLL VSSPLL VSS
-- -- --
-- -- --
-- -- --
I I I
M15 K16 A1, A10, A16, E5, E12, F6, F11, G7:10, H7:10, J1, J7:10, K7:10, L6, L11, M5, N16, R7, T1, T16 E6:8, F5, F7, F8, G5, G6, H5, H6, J11, J12, K11, K12, L9, L10, L12, M9:11
M13 L13 F7, F8, G6:9, H6:9, J7, J8
OVDD
--
--
--
I
E5:7, F5, F6, H10, J9, J10, K8:10
VDD SD_VDD
-- --
-- --
-- --
I I
D8, H13, K4, N8 D6, G5, G12, L7 E9:11, F9, F10, E8:10, F9, F10, F12, G11, G12, G10, H5, J5, J6, H11, H12, J5, K5:7 J6, K5, K6, L5, L7, L8, M6, M7, M8
1
Refers to pin's primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR, PBS, PSDRAM. 2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO module is not responsible for assigning these pins.
5
5.1
* * *
Design Recommendations
Layout
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ground planes for the MCF5275. See application note AN1259 System Design and Layout Techniques for Noise Reduction in MCU-Based Systems. Match the PC layout trace width and routing to match trace length to operating frequency and board impedance. Add termination (series or therein) to the traces to dampen reflections. Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do cross-talk
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
9
Design Recommendations
analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6 mils trace and separation. Clocks get extra separation and more precise balancing.
5.2
*
Power Supply
33uF, 0.1 F, and 0.01 F across each power supply
5.2.1
Supply Voltage Sequencing and Separation Cautions
Figure 2 shows situations in sequencing the I/O VDD (OVDD), SDRAM VDD (SDVDD), PLL VDD (PLLVDD), and Core VDD (VDD).
OVDD, SDVDD Supplies Stable 2.5V SDVDD (2.5V)
DC Power Supply Voltage
3.3V
1.5V
1
VDD, PLLVDD
2
0 Time Notes: 1. VDD should not exceed OVDD, SDVDD or PLLVDD by more than 0.4 V at any time, including power-up. 2. Recommended that VDD/PLLVDD should track OVDD/SDVDD up to 0.9 V, then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (OVDD, SDVDD, VDD, or PLLVDD) by more than 0.5 V at any time, including during power-up. 4. Use 1 ms or slower rise time for all supplies.
Figure 2. Supply Voltage Sequencing and Separation Cautions
The relationship between SDVDD and OVDD is non-critical during power-up and power-down sequences. Both SDVDD (2.5V or 3.3V) and OVDD are specified relative to VDD.
5.2.1.1
Power Up Sequence
If OVDD/SDVDD are powered up with VDD at 0 V, then the sense circuits in the I/O pads will cause all pad output drivers connected to the OVDD/SDVDD to be in a high impedance state. There is no limit on how long after OVDD/SDVDD powers up before VDD must powered up. VDD should not lead the OVDD, SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 s to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: 1. Use 1 s or slower rise time for all supplies.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 10 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Design Recommendations
2. VDD/PLLVDD and OVDD/SDVDD should track up to 0.9 V, then separate for the completion of ramps with OVDD/SD VDD going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
5.2.1.2
Power Down Sequence
If VDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after VDD and PLLVDD power down before OVDD or SDVDD must power down. VDD should not lag OVDD, SDVDD, or PLLVDD going low by more than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: 1. Drop VDD/PLLVDD to 0 V. 2. Drop OVDD/SDVDD supplies.
5.3
* *
Decoupling
Place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint of the package. 0.1 F and 0.01 F at each supply input
5.4
*
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses when excessive loading is expected. See electricals.
5.5
*
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
5.6
* * * * * * * *
Clocking Recommendations
Use a multi-layer board with a separate ground plane. Place the crystal and all other associated components as close to the EXTAL and XTAL (oscillator pins) as possible. Do not run a high frequency trace around crystal circuit. Ensure that the ground for the bypass capacitors is connected to a solid ground trace. Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop currents in the vicinity of the crystal. Tie the ground pin to the most solid ground in the system. Do not connect the trace that connects the oscillator and the ground plane to any other circuit element. This tends to make the oscillator unstable. Tie XTAL to ground when an external oscillator is clocking the device.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 11
Design Recommendations
5.7
5.7.1
5.7.1.1
Interface Recommendations
DDR SDRAM Controller
SDRAM Controller Signals in Synchronous Mode
Table 3. Synchronous DRAM Signal Connections
Signal SD_SRAS Description Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not confuse SD_SRAS with the DRAM controller's SDRAM_CS[1:0], which should not be interfaced to the SDRAM SD_SRAS signals. Synchronous column address strobe. Indicates a valid column address is present and can be latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled SD_SCAS on the SDRAM. DRAM read/write. Asserted for write operations and negated for read operations. Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals. Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can enter a power-down mode where operations are suspended or they can enter self-refresh mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external multiplexing, setting COC allows SD_CKE to provide command-bit functionality. Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs. Bus clock output. Connects to the CLK input of SDRAMs.
Table 3 shows the behavior of SDRAM signals in synchronous mode.
SD_SCAS
SD_WE SD_CS[1:0] SD_CKE
BS[3:2] DDR_CLKOUT
5.7.1.2
Address Multiplexing
See the SDRAM controller module chapter in the MCF5275 Reference Manual for details on address multiplexing.
5.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10 Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3 standard defines and the FEC module supports 18 signals. These are shown in Table 4.
Table 4. MII Mode
Signal Description Transmit clock Transmit enable Transmit data Transmit error MCF5275 Pin FECn_TXCLK FECn_TXEN FECn_TXD[3:0] FECn_TXER
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 12 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Design Recommendations
Table 4. MII Mode (continued)
Signal Description Collision Carrier sense Receive clock Receive enable Receive data Receive error Management channel clock Management channel serial data MCF5275 Pin FECn_COL FECn_CRS FECn_RXCLK FECn_RXDV FECn_RXD[3:0] FECn_RXER FECn_MDC FECn_MDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275 configuration for seven-wire serial mode connections to the external transceiver are shown in Table 5.
Table 5. Seven-Wire Mode Configuration
Signal Description Transmit clock Transmit enable Transmit data Collision Receive clock Receive enable Receive data Unused, configure as PB14 Unused input, tie to ground Unused, configure as PB[13:11] Unused output, ignore Unused, configure as PB[10:8] Unused, configure as PB15 Input after reset, connect to ground MCF5275 Pin FECn_TXCLK FECn_TXEN FECn_TXD[0] FECn_COL FECn_RXCLK FECn_RXDV FECn_RXD[0] FECn_RXER FECn_CRS FECn_RXD[3:1] FECn_TXER FECn_TXD[3:1] FECn_MDC FECn_MDIO
Refer to the M5275EVBevaluation board user's manual for an example of how to connect an external PHY. Schematics for this board are accessible at the MCF5275 site by navigating to: http://www.freescale.com/coldfire.
5.7.3
BDM
Use the BDM interface as shown in the M5275EVB evaluation board user's manual. The schematics for this board are accessible at the MCF5275 site by navigating to: http://www.freescale.com/coldfire.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 13
Mechanicals/Pinouts
6
6.1
Mechanicals/Pinouts
256 MAPBGA Pinout
Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages.
1 A VSS FEC1_ RXD3 FEC1_ TXCLK FEC1_ TXER FEC1_ TXD3 FEC1_ TXD0 FEC1_ MDIO DT1IN VSS OE SD_ SCAS D31 D30 D27 D25 VSS 1 2 FEC1_ RXD1 FEC1_ RXD2 FEC1_ RXER FEC1_ TXEN FEC1_ TXD2 FEC1_ TXD1 FEC1_ MDC DT1OUT DT2IN SD_WE SD_ SRAS SD_CS1 D29 D26 D24 SD_ VREF 2 3 FEC1_ RXDV FEC1_ RXD0 FEC0_ TXCLK FEC0_ TXER FEC0_ TXD3 FEC0_ TXD2 DT0OUT DT0IN DT2OUT DT3OUT SD_CKE BS3 D28 D23 D22 D21 3 4 FEC1_ CRS FEC1_ RXCLK FEC0_ RXER FEC0_ TXEN NC FEC0_ TXD1 FEC0_ TXD0 NC DT3IN VDD TS SD_DQS3 D20 D19 D18 D17 4 5 FEC1_ COL FEC0_ RXDV FEC0_ RXD2 FEC0_ RXD3 VSS OVDD OVDD OVDD SD_VDD SD_VDD SD_VDD VSS D16 SD_DQS2 BS2 SD_CS0 5 6 FEC0_ COL FEC0_ RXCLK FEC0_ RXD0 FEC0_ RXD1 OVDD VSS OVDD OVDD SD_VDD SD_VDD VSS SD_VDD SD_A10 TIP CS0 7 FEC0_ MDIO FEC0_ MDC FEC0_ CRS U0RTS OVDD OVDD VSS VSS VSS VSS 8 U0RXD U0TXD U0CTS VDD 9 U1RXD U1TXD U1CTS U1RTS 10 VSS I2C_ SDA I2C_ SCL CS7 11 A23 A22 A21 CS6 12 A20 A19 A18 CS5 VSS SD_VDD 13 A17 A16 A15 CS4 CS3 CS2 IRQ7 VDD IRQ2 IRQ1 TA USB_ SUSP CLK MOD1 CLK MOD0 QSPI_ CS3 QSPI_ DIN 13 14 A14 A13 A12 A7 A5 A2 USB_ SPEED IRQ4 IRQ3 15 SD_ VREF A11 A10 A6 A4 A1 USB_ CLK IRQ5 16 VSS A9 A8 TSIZ1 A3 A0 TSIZ0 IRQ6 A
B
B
C
C
D
D
E
OVDD SD_VDD SD_VDD SD_VDD OVDD SD_VDD SD_VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS OVDD OVDD VSS
E
F
F
G
SD_VDD SD_VDD SD_VDD SD_VDD OVDD OVDD VSS OVDD OVDD OVDD OVDD NC QSPI_ CS2 QSPI_ CS0 QSPI_ DOUT CLKOUT 12
G
H
H
J
USB_RP USB_RN J
K
USB_TN USB_TP VSSPLL K USB_ TXEN PLL_ TEST USB_ RXD VDDPLL EXTAL XTAL VSS
L
SD_VDD SD_VDD OVDD SD_VDD SD_VDD OVDD CS1 R/W VSS VDD RCON U2RTS TEA 8 TEST
L
M
M
N
DDATA2 DDATA0
RSTOUT RESET TRST/ DSCLK JTAG_ EN QSPI_ CS1 14 TDO/ DSO TMS/ BKPT QSPI_ CLK 15
N
P
U2CTS DDATA3 DDATA1 U2TXD U2RXD 9 PST2 PST3 10 PST0 PST1 11
TCLK/ P PSTCLK TDI/DSI R VSS 16
R
T
DDR_CLK DDR_CLK OUT OUT 6 7
T
Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 14 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanicals/Pinouts
6.2
Package Dimensions - 256 MAPBGA
Figure 6 shows MCF5275 256 MAPBGA package dimensions.
X Y
D
LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA
M K A2 A1
256X
5 0.30 Z A
E
Z
4
0.15 Z DETAIL K
ROTATED 90 CLOCKWISE NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. MILLIMETERS MIN MAX 1.25 1.60 0.27 0.47 1.16 REF 0.40 0.60 17.00 BSC 17.00 BSC 1.00 BSC 0.50 BSC
M 0.20
15X
e
METALIZED MARK FOR PIN A1 IDENTIFICATION IN THIS AREA A B C D E F G H J K L M N P R T
S
16151413121110 7654321
15X
e
S
256X
b 0.25 0.10
3
M M
ZXY Z
VIEW M-M
DIM A A1 A2 b D E e S
Figure 4. 256 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 15
Mechanicals/Pinouts
6.3
196 MAPBGA Pinout
Figure 5 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals by group and shows which signals are muxed and bonded on each of the device packages.
1 A NC FEC0_ RXD2 FEC0_ TXCLK FEC0_ TXD3 DT0IN DT1IN DT3OUT 2 FEC0_ CRS FEC0_ RXD1 FEC0_ TXER FEC0_ TXD0 DT0OUT DT1OUT DT3IN TS SD_DQS3 D29 D26 D21 D19 SD_ VREF 2 3 FEC0_ MDIO FEC0_ RXCLK FEC0_ TXEN FEC0_ TXD1 FEC0_ TXD2 DT2IN SD_CAS SD_CS1 D31 D28 D25 D18 D16 SD_DQS2 3 4 U0RXD FEC0_ COL FEC0_ RXDV FEC0_ RXD3 FEC0_ RXER DT2OUT SD_WE OE D22 D23 D24 D17 SD_A10 CS1 4 5 U0TXD U0RTS FEC0_ MDC FEC0_ RXD0 OVDD OVDD VDD SD_VDD1 6 U1RXD U1RTS U0CTS VDD OVDD OVDD VSS VSS 7 I2C_SCL I2C_SDA U1CTS U1TXD OVDD VSS VSS VSS VSS 8 A23 A22 A21 CS7 9 CS6 A20 A18 A19 10 CS5 A16 A17 CS4 11 A15 A13 A14 A11 A6 A3 USB_ SPEED IRQ4 USB_RP TDO/DSO QSPI_CLK 12 A12 CS3 A10 A7 A4 USB_CLK VDD IRQ2 USB_TP RESET RSTOUT TDI/DSI 13 SD_ VREF A9 A8 A5 A1 A0 IRQ6 USB_RN IRQ1 USB_ TXEN VSSPLL VDDPLL USB_ SUSP 14 NC TSIZ1 CS2 A2 TSIZ0 IRQ7 IRQ5 IRQ3 USB_TN TA A
B
B
C
C
D
D
E
SD_VDD2 SD_VDD2 SD_VDD2 VSS VSS VSS VSS OVDD PST2 PST1 PST0 DDATA1 8 SD_VDD2 SD_VDD2 VSS VSS OVDD OVDD DDATA0 QSPI_ CS0 QSPI_ CS2 CLKOUT 9 SD_VDD2 OVDD OVDD OVDD QSPI_ DOUT
E
F
F
G
G
H SD_SRAS SD_CKE BS3 D30 D27 D20 NC 1
H
J
SD_VDD1 SD_VDD1
J
K
SD_VDD1 SD_VDD1 SD_VDD1 BS2 SD_CS0 CS0 R/W RCON TEST VDD DDATA3 DDATA2 PST3 7
K
L
USB_RXD L EXTAL XTAL NC 14
M
QSPI_DIN CLKMOD1 QSPI_ CS1 QSPI_ CS3 10
M
N
CLKMOD0 TMS/BKPT JTAG_EN 11
N
P
DDR_CLK DDR_CLK OUT OUT 5 6
TCLK/PST TRST/DSC CLK LK 12 13
P
Figure 5. MCF5274L and MCF5275L Pinout (196 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 16 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Mechanicals/Pinouts
6.4
Package Dimensions - 196 MAPBGA
Figure 6 shows MCF5275 196 MAPBGA package dimensions.
X Y D
Laser mark for pin 1 identification in this area
M K
NOTES: 1. Dimensions are in millimeters. 2. Interpret dimensions and tolerances per ASME Y14.5M, 1994. 3. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z. 4. Datum Z (seating plane) is defined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package.
E Millimeters DIM Min A A1 A2 M TOL 13X e S
14 13 12 11 10 9 6 5 4 3 2 1 A B C D E F G H J K L M N P 1.25 0.27
Max
1.60 0.47
1.16 REF 0.45 0.55
b D E
15.00 BSC 15.00 BSC 1.00 BSC 0.50 BSC
Metalized mark for pin 1 identification in this area
e S
5 A A2 0.20 Z
S 13X e
A1
Z
4
0.10 Z 196X
Detail K Rotated 90 Clockwise
3 196X b 0.15 Z X Y 0.08 Z View M-M
Figure 6. 196 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 17
Ordering Information
7
Ordering Information
Table 6. Orderable Part Numbers
Freescale Part Number MCF5274LVM133 MCF5274LVM166 MCF5274VM133 MCF5274VM166 MCF5275LCVM133 MCF5275LCVM166 MCF5275CVM133 MCF5275CVM166 Description MCF5274L RISC Microprocessor, 196 MAPBGA MCF5274L RISC Microprocessor, 196 MAPBGA MCF5274 RISC Microprocessor, 256 MAPBGA MCF5274 RISC Microprocessor, 256 MAPBGA MCF5275L RISC Microprocessor, 196 MAPBGA MCF5275L RISC Microprocessor, 196 MAPBGA MCF5275 RISC Microprocessor, 256 MAPBGA MCF5275 RISC Microprocessor, 256 MAPBGA Speed 133MHz 166MHz 133MHz 166MHz 133MHz 166MHz 133MHz 166MHz Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
8
Preliminary Electrical Characteristics
This appendix contains electrical specification tables and reference timing diagrams for the MCF5275 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5275. The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however for production silicon these specifications will be met. Finalized specifications will be published after complete characterization and device qualifications have been completed. NOTE The parameters specified in this appendix supersede any values found in the module specifications.
8.1
Maximum Ratings
Table 7. Absolute Maximum Ratings1, 2
Rating Core Supply Voltage I/O Pad Supply Voltage (3.3V) Memory Interface SSTL 2.5V Pad Supply Voltage Memory Interface SSTL 3.3V Pad Supply Voltage PLL Supply Voltage Digital Input Voltage 3 EXTAL pin voltage XTAL pin voltage Symbol VDD OVDD SDVDD SDVDD VDDPLL VIN VEXTAL VXTAL Value - 0.5 to +2.0 - 0.3 to +4.0 - 0.3 to + 2.8 - 0.3 to +4.0 - 0.3 to +4.0 - 0.3 to + 4.0 0 to 3.3 0 to 3.3 Unit V V V V V V V V
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 18 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 7. Absolute Maximum Ratings1, 2 (continued)
Rating Instantaneous Maximum Current Single pin limit (applies to all pins) 4, 5 Operating Temperature Range (Packaged) Storage Temperature Range
1
Symbol ID TA (TL - TH) Tstg
Value 25 - 40 to 85 - 65 to 150
Unit mA C C
2
3
4 5
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or O VDD). Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. All functional non-supply pins are internally clamped to VSS and O VDD. Power supply must maintain regulation within operating O VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the injection current may flow out of O VDD and could result in external power supply going out of regulation. Insure external O VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions.
8.2
Thermal Characteristics
Table 8. Thermal characteristics
Characteristic Symbol Four layer board (2s2p) Four layer board (2s2p) JMA JMA JB JC Natural convection jt Tj 256MBGA 261,2 231,2 153 104 21,5 105 196MBGA 321,2 291,2 20
3
Table 8 lists thermal resistance values
Unit C/W C/W C/W C/W C/W
oC
Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction to top of package Maximum operating junction temperature
1
104 21,5 105
JMA and jt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection. Freescale recommends the use of JmA and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specification. System designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the device junction temperature specification can be verified by physical measurement in the customer's system using the jt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2. 2 Per JEDEC JESD51-6 with the board horizontal. 3 Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 19
Preliminary Electrical Characteristics
5
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written in conformance with Psi-JT. The average chip-junction temperature (TJ) in C can be obtained from: T J = T A + ( P D x JMA ) (1) Where: TA JMA PD PINT PI/O = Ambient Temperature, C = Package Thermal Resistance, Junction-to-Ambient, C/W = PINT + PI/O = IDD x VDD, Watts - Chip Internal Power = Power Dissipation on Input and Output Pins -- User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is neglected) is: P D = K / ( T J + 273C ) Solving equations 1 and 2 for K gives: K = PD x (TA + 273 C) + JMA x PD 2 (3) where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. (2)
8.3
ESD Protection
Table 9. ESD Protection Characteristics1, 2
Characteristics ESD Target for Human Body Model ESD Target for Machine Model HBM Circuit Description MM Circuit Description Number of pulses per pin (HBM) positive pulses negative pulses Number of pulses per pin (MM) positive pulses negative pulses Interval of Pulses
1
Symbol HBM MM Rseries C Rseries C -- -- -- -- --
Value 2000 200 1500 100 0 200 1 1
Units V V pF pF --
-- 3 3 1 sec
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 20 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
8.4
DC Electrical Specifications
Table 10. DC Electrical Specifications1
Characteristic Symbol VDD OVDD SDVDD SDVDD VREF VREF VIH VIL VOH VOL VHYS VIH VIL VOH VOL Iin IOZ IAPU Cin -- -- CL IDD -- -- -- -- OIDD -- -- IIC -1.0 -10 1.0 10 250 250 mA A mA 175 15 10 100 mA mA mA A 7 7 pF 25 50 Min 1.4 3.0 2.3 3.0 0.5 SD VDD 0.45 SD VDD 0.7 x OVDD VSS - 0.3 OVDD - 0.5 -- 0.06 x VDD VREF + 0.3 VSS - 0.3 SDVDD - 0.25V -- -1.0 -1.0 -10 Max 1.6 3.6 2.7 3.6 --2 --2 3.6 0.35 x OVDD -- 0.5 -- SDVDD + 0.3 VREF - 0.3 -- 0.35 1.0 1.0 -130 Unit V V V V V V V V V V mV V V V V A A A pF
Core Supply Voltage I/O Pad Supply Voltage SSTL I/O Pad Supply Voltage SSTL I/O Pad Supply Voltage SSTL Memory pads reference voltage (SD VDD = 2.5V) SSTL Memory pads reference voltage (SD VDD = 3.3V) Input High Voltage 3.3V I/O Pads Input Low Voltage 3.3V I/O Pads Output High Voltage 3.3V I/O Pads IOH = -2.0 mA Output Low Voltage 3.3V I/O Pads IOL = 2.0mA Input Hysteresis 3.3V I/O Pads Input High Voltage SSTL 3.3V/2.5V3 Input Low Voltage SSTL 3.3V/2.5V3 Output High Voltage SSTL 3.3V/2.5V4 IOH = -5.0 mA Output Low Voltage SSTL 3.3V/2.5V4 IOL = 5.0 mA Input Leakage Current Vin = VDD or VSS, Input-only pins High Impedance (Off-State) Leakage Current Vin = VDD or VSS, All input/output and output pins Weak Internal Pull Up Device Current, tested at VIL Max.5 Input Capacitance All input-only pins All input/output (three-state) pins Load Capacitance7 Low Drive Strength High Drive Strength Core Operating Supply Current 8 Master Mode WAIT DOZE STOP I/O Pad Operating Supply Current Master Mode Low Power Modes DC Injection Current 3, 9, 10, 11 VNEGCLAMP =VSS- 0.3 V, VPOSCLAMP = VDD + 0.3 Single Pin Limit Total MCU Limit, Includes sum of all stressed pins
1 2 6
Refer to Table 11 for additional PLL specifications. VREF is specified as a nominal value only instead of a range, so no maximum value is listed. 3 This specification is guaranteed by design and is not 100% tested. MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
Preliminary--Subject to Change Without Notice
21
Preliminary Electrical Characteristics
4
The actual VOH and VOL values for SSTL pads are dependent on the termination and drive strength used. The specifications numbers assume no parallel termination. 5 Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices. 6 This parameter is characterized before qualification rather than 100% tested. 7 pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive strength and termination. 8 Current measured at maximum system clock frequency, all modules active, and default drive strength with matching load. 9 All functional non-supply pins are internally clamped to VSS and their respective VDD. 10 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 11 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
8.5
Oscillator and Phase Lock Loop (PLLMRFM) Electrical Specifications
Table 11. PLL Electrical Specifications1
Characteristic Symbol fref_crystal fref_ext fref_1:1 fcore 0 fref / 32 100 TBD -- TBD TBD TBD TBD TBD VOL -- 5 tlpll Time 6, 9 tlplk -- -- 11 750 ms s -- TBD 30 750 pF s Min 8 8 24 Max 25 25 83 166 83 83 1000 TBD 10 TBD TBD V TBD TBD V -- V MHz MHz MHz kHz MHz ms V Unit MHz
PLL Reference Frequency Range Crystal reference External reference 1:1 Mode (NOTE: fsys/2 = 2 x fref_1:1) Core frequency CLKOUT Frequency 2 External reference On-Chip PLL Frequency Loss of Reference Frequency 3, 5 Self Clocked Mode Frequency Crystal Start-up Time
5, 6 4, 5
fsys/2 fLOR fSCM tcst VIHEXT VIHEXT VILEXT VILEXT VOH
EXTAL Input High Voltage Crystal Mode All other modes (Dual Controller (1:1), Bypass, External) EXTAL Input Low Voltage Crystal Mode All other modes (Dual Controller (1:1), Bypass, External) XTAL Output High Voltage IOH = 1.0 mA XTAL Output Low Voltage IOL = 1.0 mA XTAL Load Capacitance7 PLL Lock Time
8
Power-up To Lock With Crystal Reference Without Crystal Reference10
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 22 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 11. PLL Electrical Specifications1 (continued)
Characteristic 1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11 Duty Cycle of reference
5
Symbol tskew tdc fUL fLCK Cjitter
Min -1 40 -3.8 -1.7 -- --
Max 1 60 4.1 2.0 5 .01 2.2 83
Unit ns % fsys/2 % fsys/2 % fsys/2 % fsys/2 % fsys/2 MHz
Frequency un-LOCK Range Frequency LOCK Range CLKOUT Period Jitter, Measured at fsys/2 Max Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Frequency Modulation Range Limit14, 15 (fsys/2Max must not be exceeded) ICO Frequency. fico = fref * 2 * (MFD+2)16
1 2 3 4 5 6 7 8 9 5, 6, 9,12, 13
Cmod fico
0.8 48
10 11 12
13 14 15 16
All values given are initial design targets and subject to change. All internal registers retain data at 0 Hz. "Loss of Reference Frequency" is the reference frequency detected internally, which transitions the PLL into self clocked mode. Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR with default MFD/RFD settings. This parameter is guaranteed by characterization before qualification rather than 100% tested. Proper PC board layout procedures must be followed to achieve specifications. Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR). Assuming a reference is available at power up, lock time is measured from the time VDD and VDDPLL are valid to RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time must be added to the PLL lock time to determine the total start-up time. tlpll = (64 * 4 * 5 + 5 x ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and = 1.57x10-6 x 2(MFD + 2) PLL is operating in 1:1 PLL mode. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the jitter percentage for a given interval. Based on slow system clock of 33MHz maximum frequency. Modulation percentage applies over an interval of 10s, or equivalently the modulation rate is 100KHz. Modulation rate selected must not result in fsys/2 value greater than the fsys/2 maximum specified value. Modulation range determined by hardware design. fsys/2 = fico / (2 * 2RFD)
8.6
External Interface Timing Characteristics
NOTE All processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the rising edge of a reference clock. The reference clock is the CLKOUT output. All other timing relationships can be derived from these values.
Table 12 lists processor bus input timings.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 23
Preliminary Electrical Characteristics
Table 12. Processor Bus Input Timing Specifications
Name B0 CLKOUT Control Inputs B1a B1b B2a B2b Control input valid to CLKOUT high2 BKPT valid to CLKOUT high
3
Characteristic1
Symbol tCYC
Min 12
Max Unit -- ns
tCVCH tBKVCH tCHCII tBKNCH
9 9 0 0
-- -- -- --
ns ns ns ns
CLKOUT high to control inputs invalid2 CLKOUT high to asynchronous control input BKPT invalid3 Data Inputs
B4 B5
1 2
Data input (D[31:16]) valid to CLKOUT high CLKOUT high to data input (D[31:16]) invalid
tDIVCH tCHDII
4 0
-- --
ns ns
Timing specifications have been indicated taking into account the full drive strength for the pads. TEA and TA pins are being referred to as control inputs. 3 Refer to figure A-19.
Timings listed in Table 12 are shown in Figure 7.
* The timings are also valid for inputs sampled on the negative clock edge. CLKOUT (83MHz) TSETUP THOLD Invalid trise
Input Setup And Hold
Invalid
Valid
Input Rise Time
Vh = VIH Vl = VIL
Input Fall Time
Vh = VIH Vl = VIL
tfall
CLKOUT
B4 B5
Inputs
Figure 7. General Input Timing Requirements
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 24 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
8.7
Processor Bus Output Timing Specifications
Table 13. External Bus Output Timing Specifications
Table 13 lists processor bus output timings.
Name
Characteristic Control Outputs
Symbol
Min
Max
Unit
B6a B6b B6c B7 B7a
CLKOUT high to chip selects (CS[7:0]) valid 1 CLKOUT high to byte enables (BS[3:2]) valid2 CLKOUT high to output enable (OE) valid3 CLKOUT high to control output (BS[3:2], OE) invalid CLKOUT high to chip selects invalid
tCHCV tCHBV tCHOV tCHCOI tCHCI
-- -- -- 0.5tCYC + 1.0 0.5tCYC + 1.0
0.5tCYC + 5.5 0.5tCYC + 5.5 0.5tCYC + 5.5 -- --
ns ns ns ns ns
Address and Attribute Outputs B8 B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) valid CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid Data Outputs B11 B12 B13
1 2
tCHAV tCHAI
-- 1.0
9 --
ns ns
CLKOUT high to data output (D[31:16]) valid CLKOUT high to data output (D[31:16]) invalid CLKOUT high to data output (D[31:16]) high impedance
tCHDOV tCHDOI tCHDOZ
-- 1.0 --
9 -- 9
ns ns ns
CS transitions after the falling edge of CLKOUT. BS transitions after the falling edge of CLKOUT. 3 OE transitions after the falling edge of CLKOUT.
Read/write bus timings listed in Table 13 are shown in Figure 8, Figure 9, and Figure 10.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 25
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT B7a CSn A[23:0] TSIZ[1:0] TS TIP B8 B6c OE B8 R/W (H) B6b BS[3:2] D[31:16] B4 B5 TA (H) B7 B11 B12 B6b B7 B9 B7 B0 B7a B6a B8 B9
B6a
B8
B8 B9 B8
B9 B9
B13
TEA (H)
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 13.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 26 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics S0 CLKOUT CSn B6a
B7a
S1
S2
S3
S4
S5
S0
S1
B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP OE B6c B7 R/W (H) B9
B9
B9
BS[3:2]
B6b B5 B4
B7
D[31:16] TA B1a B2a
TEA (H)
Figure 9. SRAM Read Bus Cycle Terminated by TA
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 13.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 27
Preliminary Electrical Characteristics
S0
CLKOUT B6a CSn B8 A[23:0] TSIZ[1:0] B8 TS B8 TIP B6c OE B9
S1
S2
S3
S4
S5
S0
S1
B7a
B9
B9
B7
R/W (H) B6b BS[3:2] D[31:16] B7
TA (H)
B1a TEA B2a
Figure 10. SRAM Read Bus Cycle Terminated by TEA
8.8
DDR SDRAM AC Timing Characteristics
The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is available and is user programmable. DDR Clock timing specifications are given in Table 14 and Figure 11.
Table 14. DDR Clock Timing Specifications1
Symbol VMP VOUT VID VIX Characteristic Clock output mid-point voltage Clock output voltage level Clock output differential voltage (peak to peak swing) Clock crossing point voltage Min 1.05 -0.3 0.7 1.05 Max 1.45 SDVDD + 0.3 SDVDD + 0.6 1.45 Unit V V V V
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 28 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
1
SD VDD is nominally 2.5V. SDCLK VIX VMP VIX SDCLK VID
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 15 must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 15. DDR Timing
NUM DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 DD16
1 2 3 4 5 6
Characteristic1 Frequency of operation Pulse Width High3 Pulse Width Low3 DDR_CLKOUT high to DDR address, SD_CKE, SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid DDR_CLKOUT high to DDR address, SD_CKE, SD_CS, SD_SCAS, SD_SRAS, SD_WE invalid Write command to first SD_DQS Latching Transition SD_DQS high to Data and DM valid (write) - setup4,5 SD_DQS high to Data and DM invalid (write) SD_DQS high to Data valid (read) - setup6 SD_DQS high to Data invalid (read) hold7 SD_DQS falling edge to CLKOUT high - setup SD_DQS falling edge to CLKOUT high - hold DQS input read preamble width (tRPRE) DQS input read postamble width (tRPST) DQS output write preamble width (tWPRE) DQS output write postamble width (tWPST) hold4
2
Symbol tCK tCKH tCKl tCMV tCMH tDQSS tQS tQH tIS tIH tDSS tDSH tRPRE tRPST tWPRE tWPST
Min TBD 12 0.45 0.45 -- 2 -- 1.5 1 -- 0.25 x tCK + 1 0.5 0.5 0.9 0.4 0.25 0.4
Max 83 TBD 0.55 0.55 0.5 x tCK + 1 -- 1.25 -- -- 1 -- -- -- 1.1 0.6 -- 0.6
Unit MHz ns tCK tCK ns ns tCK ns ns ns ns ns ns tCK tCK tCK tCK
Clock Period (DDR_CLKOUT)
7
All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins. DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core. tCKH + tCKL must be less than or equal to tCK. D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2. The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The remaining data beats will be valid for each subsequent SD_DQS edge Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or other factors). Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data line becomes invalid.
Figure 13 shows a DDR SDRAM write cycle.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 29
Preliminary Electrical Characteristics
DDR_CLKOUT VIX VMP VIX DDR_CLKOUT
VID
Figure 12. DDR_CLKOUT and DDR_CLKOUT Crossover Timing
DD1 DDR_CLKOUT
DD2
DD3 DDR_CLKOUT
DD5 SD_CSn,SD_WE, SD_SRAS,SD_SCAS DD4 A[13:0]
CMD
DD6
ROW
COL
DD7
DM[3:2] DD8 SD_DQS[3:2] DD7 D[31:16]
WD1 WD2 WD3 WD4
DD8
Figure 13. DDR Write Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 30 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
DD1 CLKOUT
DD2
DD3 CLKOUT
DD5 SD_CSn,SD_WE, SD_SRAS,SD_SCAS DD4 A[13:0]
CL=2
CMD CL=2.5 ROW COL DQS Read Preamble
DD10 DD9
SD_DQS[3:2] CL = 2
DQS Read Postamble
D[31:16]
SD_DQS[3:2] CL = 2.5
WD1 WD2 WD3 WD4 DQS Read DQS Read Preamble Postamble
D[31:16]
WD1 WD2 WD3 WD4
Figure 14. DDR Read Timing
8.9
General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1, Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in Table 16 and Figure 15.
Table 16. GPIO Timing
NUM G1 G2 G3 G4 Characteristic CLKOUT High to GPIO Output Valid CLKOUT High to GPIO Output Invalid GPIO Input Valid to CLKOUT High CLKOUT High to GPIO Input Invalid Symbol tCHPOV tCHPOI tPVCH tCHPI Min -- 1.0 9 1.5 Max 10 -- -- -- Unit ns ns ns ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 31
Preliminary Electrical Characteristics
CLKOUT
G1 G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 15. GPIO Timing
8.10
Reset and Configuration Override Timing
Table 17. Reset and Configuration Override Timing (VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM R1 R2 R3 R4 R5 R6 R7 R8
1 2
Characteristic RESET Input valid to CLKOUT High CLKOUT High to RESET Input invalid RESET Input valid Time
2
Symbol tRVCH tCHRI tRIVT tCHROV tROVCV tCOS tCOH tROICZ
Min 9 1.5 5 -- 0 20 0 --
Max -- -- -- 10 -- -- -- 1 x tCYC
Unit ns ns tCYC ns ns tCYC ns ns
CLKOUT High to RSTOUT Valid RSTOUT valid to Config. Overrides valid Configuration Override Setup Time to RSTOUT invalid Configuration Override Hold Time after RSTOUT invalid RSTOUT invalid to Configuration Override High Impedance
All AC timing is shown with respect to 50% OVDD levels unless otherwise noted. During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously to the system. Thus, RESET must be held a minimum of 100 ns.
CLKOUT
R1 R2 R3 R4 R4 R8 R5 Configuration Overrides1: (RCON, Override pins]) R6 R7
RESET
RSTOUT
1. Refer to the Coldfire Integration Module (CIM) section for more information.
RESET and Configuration Override Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 32 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
8.11
Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
8.11.1
MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK)
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FECn_RXCLK frequency. Table 18 lists MII receive channel timings.
Table 18. MII Receive Signal Timing
Num M1 M2 M3 M4 Characteristic FECn_RXD[3:0], FECn_RXDV, FECn_RXER to FECn_RXCLK setup FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV, FECn_RXER hold FECn_RXCLK pulse width high FECn_RXCLK pulse width low Min 5 5 35% 35% Max -- -- 65% 65% Unit ns ns FECn_RXCLK period FECn_RXCLK period
Figure 16 shows MII receive signal timings listed in Table 18.
M3 M4
FECn_RXCLK (input) FECn_RXD[3:0] (inputs) FECn_RXDV FECn_RXER M1 M2
Figure 16. MII Receive Signal Timing Diagram
8.11.2
MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK)
Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FECn_TXCLK frequency.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 33
Preliminary Electrical Characteristics
Table 19. MII Transmit Channel Timing
Num M5 M6 M7 M8 Characteristic FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER invalid FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN, FECn_TXER valid FECn_TXCLK pulse width high FECn_TXCLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns FECn_TXCLK period FECn_TXCLK period
Figure 17 shows MII transmit signal timings listed in Table 19.
M7 M8
FECn_TXCLK (input) M5 FECn_TXD[3:0] (outputs)
FECn_TXEN
FECn_TXER M6
Figure 17. MII Transmit Signal Timing Diagram
8.11.3
MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
Table 20. MII Asynchronous Input Signal Timing
Table 20 lists MII asynchronous inputs signal timing.
Num M9
Characteristic FECn_CRS, FECn_COL minimum pulse width
Min 1.5
Max --
Unit FECn_TXCLK period
Figure 18 shows MII asynchronous input timings listed in Table 20.
FECn_CRS FECn_COL M9
Figure 18. MII Async Inputs Timing Diagram
8.11.4
MII Serial Management Channel Timing (FECn_MDIO and FECn_MDC)
Table 21 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 34 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 21. MII Serial Management Channel Timing
Num M10 M11 M12 M13 M14 M15 Characteristic FECn_MDC falling edge to FECn_MDIO output invalid (minimum propagation delay) FECn_MDC falling edge to FECn_MDIO output valid (max prop delay) FECn_MDIO (input) to FECn_MDC rising edge setup FECn_MDIO (input) to FECn_MDC rising edge hold FECn_MDC pulse width high FECn_MDC pulse width low Min 0 -- 10 0 40% 40% Max -- 25 -- -- 60% 60% Unit ns ns ns ns MDC period MDC period
Figure 19 shows MII serial management channel timings listed in Table 21.
M14 FECn_MDC (output) M15
M10
FECn_MDIO (output)
M11
FECn_MDIO (input)
M12
M13
Figure 19. MII Serial Management Channel Timing Diagram
8.11.5
USB Interface AC Timing Specifications
Table 22. USB Interface Timing
Num US1 US2 US3 US4 Characteristic USB_CLK frequency of operation USB_CLK fall time (VIH = 2.4 V to VIL = 0.5 V) USB_CLK rise time (VIL = 0.5 V to VIH = 2.4 V) USB_CLK duty cycle (at 0.5 x O VDD) Data Inputs US5 USB_RP, USB_RN, USB_RXD valid to USB_CLK high 6 -- ns Min 48 -- -- 45 Max 48 2 2 55 Units MHz ns ns %
Table 22 lists USB Interface timings.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 35
Preliminary Electrical Characteristics
Table 22. USB Interface Timing (continued)
Num US6 Characteristic USB_CLK high to USB_RP, USB_RN, USB_RXD invalid Data Outputs US7 US8 USB_CLK high to USB_TP, USB_TN, USB_SUSP valid USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid -- 3 12 -- ns ns Min 6 Max -- Units ns
Figure 20 shows USB interface timings listed in Table 22.
US1
USB_CLK
US7 USB Outputs
US8
US5 USB Inputs
US6
trise Input Rise Time Vh = VIH Vl = VIL tfall Input Fall Time Vh = VIH Vl = VIL
Figure 20. USB Signals Timing Diagram
8.12
I2C Input/Output Timing Specifications
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num I1 I2 I3 I4 I5 I6 I7 Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Min 2 x tCYC 8 x tCYC -- 0 -- 4 x tCYC 0 Max -- -- 1 -- 1 -- -- Units ns ns ms ns ms ns ns
Table 23 lists specifications for the I2C input timing parameters shown in Figure 21.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 36 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 23. I2C Input Timing Specifications between I2C_SCL and I2C_SDA (continued)
Num I8 I9 Characteristic Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 x tCYC 2 x tCYC Max -- -- Units ns ns
Table 24 lists specifications for the I2C output timing parameters shown in Figure 21.
Table 24. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num I11 I2 I3
1 2
Characteristic Start condition hold time Clock low period I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V) Data hold time I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V) Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time
Min 6 x tCYC 10 x tCYC -- 7 x tCYC -- 10 x tCYC 2 x tCYC 20 x tCYC 10 x tCYC
Max -- -- -- -- 3 -- -- -- --
Units ns ns s ns ns ns ns ns ns
I4 1 I5 3 I6 1 I7 1 I8
1
I9 1
1
Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in Table 24. The I2C interface is designed to scale the actual data transition time to move it to the middle of the I2C_SCL low period. The actual position is affected by the prescale and division values programmed into the IFDR; however, the numbers given in Table 24 are minimum values. 2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 Specified at a nominal 50-pF load.
Figure 21 shows timing for the values in Table 23 and Table 24.
I2 SCL I6 I5
I1
I4
I7
I8
I3
I9
SDA
Figure 21. I2C Input/Output Timings
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 37
Preliminary Electrical Characteristics
8.13
DMA Timers Timing Specifications
Table 25. Timer Module AC Timing Specifications
Name T1 T2 Characteristic 1 T0IN / T1IN / T2IN / T3IN cycle time T0IN / T1IN / T2IN / T3IN pulse width Min 3 x tCYC 1 x tCYC Max -- -- Unit ns ns
1
All timing references to CLKOUT are given to its rising edge.
8.14
Name QS1 QS2 QS3 QS4 QS5
QSPI Electrical Specifications
Table 26. QSPI Modules AC Timing Specifications
Characteristic QSPI_CS[3:0] to QSPI_CLK QSPI_CLK high to QSPI_DOUT valid. QSPI_CLK high to QSPI_DOUT invalid (Output hold) QSPI_DIN to QSPI_CLK (Input setup) QSPI_DIN to QSPI_CLK (Input hold) Min 1 -- 2 9 9 Max 510 10 -- -- -- Unit tCYC ns ns ns ns
QS1 QSPI_CS[3:0]
QSPI_CLK QS2 QSPI_DOUT QS3 QSPI_DIN QS4 QS5
Figure 22. QSPI Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 38 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
8.15
Num J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14
1
JTAG and Boundary Scan Timing
Table 27. JTAG and Boundary Scan Timing
Characteristics1 TCLK Frequency of Operation TCLK Cycle Period TCLK Clock Pulse Width TCLK Rise and Fall Times Boundary Scan Input Data Setup Time to TCLK Rise Boundary Scan Input Data Hold Time after TCLK Rise TCLK Low to Boundary Scan Output Data Valid TCLK Low to Boundary Scan Output High Z TMS, TDI Input Data Setup Time to TCLK Rise TMS, TDI Input Data Hold Time after TCLK Rise TCLK Low to TDO Data Valid TCLK Low to TDO High Z TRST Assert Time TRST Setup Time (Negation) to TCLK High Symbol fJCYC tJCYC tJCW tJCRF tBSDST tBSDHT tBSDV tBSDZ tTAPBST tTAPBHT tTDODV tTDODZ tTRSTAT tTRSTST Min DC 4 x tCYC 26 0 4 26 0 0 4 10 0 0 100 10 Max 1/4 -- -- 3 -- -- 33 33 -- -- 26 8 -- -- Unit fsys/2 ns ns ns ns ns ns ns ns ns ns ns ns ns
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J2 J3 J3
TCLK (input)
J4
VIH VIL J4
Figure 23. Test Clock Input Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 39
Preliminary Electrical Characteristics
TCLK
VIL J5
VIH J6
Data Inputs
J7
Input Data Valid
Data Outputs
J8
Output Data Valid
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 24. Boundary Scan (JTAG) Timing
TCLK
VIL J9
VIH J10
TDI TMS
J11
Input Data Valid
TDO
J12
Output Data Valid
TDO
J11
TDO
Output Data Valid
Figure 25. Test Access Port Timing
TCLK
14
TRST
13
Figure 26. TRST Timing
8.16
Debug AC Timing Specifications
Table 28 lists specifications for the debug AC timing parameters shown in Figure 28.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 40 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Preliminary Electrical Characteristics
Table 28. Debug AC Timing Specification
166 MHz Num D0 D1 D2 D3 D4 1 D5 D6 D7 D8
1
Characteristic Min PSTCLK cycle time PST, DDATA to PSTCLK setup CLKOUT to PST, DDATA hold DSI-to-DSCLK setup DSCLK-to-DSO hold DSCLK cycle time BKPT input data setup time to PSTCLK Rise BKPT input data hold time to PSTCLK Rise PSTCLK high to BKPT high Z -- 4 1.0 1 x tCYC 4 x tCYC 5 x tCYC 4 1.5 0.0 Max 0.5 -- -- -- -- -- -- -- 10.0
Units tCYC ns ns ns ns ns ns ns ns
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input relative to the rising edge of PSTCLK.
Figure 27 shows real-time trace timing for the values in Table 28.
PSTCLK
D1 D2
PST[3:0] DDATA[3:0]
Figure 27. Real-Time Trace AC Timing
Figure 28 shows BDM serial port AC timing for the values in Table 28.
PSTCLK
D5
DSCLK
D3
DSI
Current
D4
Next
DSO
Past
Current
Figure 28. BDM Serial Port AC Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 41
Documentation
9
Documentation
Documentation regarding the MCF5275 and their development support tools is available from a local Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center, or through the Freescale web address at http://www.freescale.com/coldfire.
10
Revision History
Table 29. Document Revision History
Rev. No. 0 1 1.1 1.2 * Initial release. * Added Figure 6. * Removed duplicate information in the module description sections. The information is all in the Signals Description Table. * Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address Multiplexing sections. This information can be found in the MCF5275 Reference Manual. * Removed list of documentation in Section 9, "Documentation.". An up-to-date list is always available on our web site. * Changed CLKOUT -> PSTCLK in Section 8.16, "Debug AC Timing Specifications." * Table 10: Update VDD spec from 1.35-1.65 to 1.4-1.6. * Table 13: Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated: B6a, B6b, B6c maximum changed from "0.5tCYC + 5" to "0.5tCYC + 5.5" B7, B7a minimum changed from "0.5tCYC + 1.5" to "0.5tCYC + 1.0" B9, B11 minimum changed from "1.5" to "1.0" * Added Section 5.2.1, "Supply Voltage Sequencing and Separation Cautions." * Added thermal characteristics for 196 MAPBGA in Table 8. * Updated package dimensions drawing, Figure 6. * Removed second sentence from Section 8.11.1, "MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK)," and Section 8.11.2, "MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK)," regarding no minimum frequency requirement for TXCLK. * Removed third and fourth paragraphs from Section 8.11.2, "MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK)," as this feature is not supported on this device. Substantive Change(s)
Table 29 provides a revision history for this hardware specification.
1.3
2
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 42 Preliminary--Subject to Change Without Notice Freescale Semiconductor
Revision History
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2 Freescale Semiconductor Preliminary--Subject to Change Without Notice 43
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Rev. 2 08/2006
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